Low core data path operating frequencies can provide significant power reduction as well as relaxed circuit design requirements for power critical dynamic random access memory (DRAM) systems. However, it is difficult to maintain a low latency high performance output channel data rate since several slower data streams must be multiplexed and level shifted into the output channel in as few stages as possible. Therefore, a practical architecture for a multi-data stream environment is desirable.
Referring to FIG. 1, there is shown a conventional output subsystem 100 comprising a plurality of preconditioning driver circuits 102, a plurality of cross-coupled transistor stacks 104, a first current source 106, a first pair of resistive loads 108, a pair of transistors 110 forming a differential output driver, a second pair of resistive loads 112, and a second current source 114. Each of the plurality of preconditioning driver circuits 102 receives an input data signal (e.g., D1) and quadrature clock signals (i.e., CLKI, /CLKI, CLKQ, and /CLKQ), and generates a pair of output data signals that are phase shifted 90° based thereon.
Referring to FIG. 2, there is shown a preconditioning driver circuit 200 that may be used as one or more of the plurality of preconditioning driver circuits 102 shown in FIG. 1. The preconditioning driver circuit 200 comprises a plurality of inverter devices 202, as well as a plurality of transmission gates each comprising an NMOS transistor 204 and a PMOS transistor 206. As described above with reference to FIG. 1, the preconditioning driver circuit 200 receives an input data signal (e.g., D1) and quadrature clock signals (i.e., CLKI, /CLKI, CLKQ, and /CLKQ), and generates a pair of output data signals (D1A and D1B) that are phase shifted 90° based thereon.
Referring again to FIG. 1, each pair of 90° phase shifted output data signals that are generated by a respective one of the plurality of preconditioning driver circuits 102 are provided to a respective one of the plurality of cross-coupled transistor stacks 104. Each of the plurality of cross-coupled transistor stacks 104 receives a pair of 90° phase shifted output data signals from a respective one of the plurality of preconditioning driver circuits 102, and generates an output driver control signal via current paths formed with the first current source 106 and one of the first pair of resistive loads 108. A complement of each output driver control signal is also generated by a corresponding one of the plurality of cross-coupled transistor stacks 104 such that four pairs of complementary output driver control signals are generated by the entire plurality of cross-coupled transistor stacks 104.
Referring to FIG. 3, there is shown a cross-coupled transistor stack 300 that may be used as one or more of the plurality of cross-coupled transistor stacks 104 shown in FIG. 1. The cross-coupled transistor stack 300 comprises a plurality of NMOS transistors 302 electrically connected in a cross-coupled manner. As described above with reference to FIG. 1, the cross-coupled transistor stack 300 receives a pair of 90° phase shifted output data signals (DA and DB) from a respective one of the plurality of preconditioning driver circuits 102, and generates an output driver control signal via current paths formed with the first current source 106 and one of the first pair of resistive loads 108.
Referring again to FIG. 1, each pair of complementary output driver control signals generated by a corresponding pair of cross-coupled transistor stacks 104 is provided as inputs to the pair of transistors 110 forming the differential output driver. The pair of transistors 110 forming the differential output driver receive each pair of complementary output driver control signals generated by a corresponding pair of cross-coupled transistor stacks 104, and generate a pair of differential output signals (DQ and DQN) via current paths formed with the second current source 114 and the second pair of resistive loads 112.
The conventional output subsystem 100 is typically designed with a logic process where threshold voltages for NMOS transistors are relatively low and thus multiple transistor stacks are allowed. However, larger threshold voltages for NMOS transistors in other logic processes may make saturation margins difficult to meet. In addition, larger current draws required to drive larger differential output driver transistors would cause transistor sizes in the cross-coupled transistor stacks to grow, due to poor IDS characteristics. This would result in excessive drain-bulk parasitic capacitance values which would preclude the use of a similar architecture. Increasing transistor sizes in the cross-coupled transistor stacks to compensate for a larger capacitive load would simply increase the drain-bulk capacitance load, thus essentially resulting in a zero-sum gain.
Referring to FIG. 4, there is shown an alternative output subsystem 400, which is essentially identical to the conventional output subsystem 100 of FIG. 1 except for the connection of the first pair of resistive loads 108 to VDD instead of VDDIO and the addition of a pair of common-source amplifiers 402. The connection of the first pair of resistive loads 108 to VDD instead of VDDIO allows the plurality of cross-coupled transistor stacks 104 to have a larger overhead voltage and makes it easier to keep the transistors in the plurality of cross-coupled transistor stacks 104 in saturation. A level shift towards VDDIO is accomplished through the pair of common-source amplifiers 402. For example, referring to FIG. 5, there is shown a common-source amplifier 500 comprising a PMOS transistor 502 and an NMOS transistor 504. However, the power consumption of such a common-source amplifier 500 would cause the output subsystem 500 to reach approximately 60 milliwatt (mW) stand-by power, which is not acceptable in many applications.
In view of the foregoing, it would be desirable to provide an output subsystem which overcomes the above-described inadequacies and shortcomings.